1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of bipolar transistors.
2. Background Art
Bipolar transistors can be integrated with CMOS transistors on the same die to provide circuits that combine the advantages of high speed and high frequency provided by bipolar transistors with the advantages of low power consumption and high noise immunity typically provided by CMOS transistors. For example, an NPN silicon-germanium (“SiGe”) heterojunction bipolar transistor, used as an example in the present application, and a CMOS transistor, such as a PFET, can be fabricated on the same substrate of a semiconductor die using a Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) process.
However, the process flow utilized to fabricate bipolar transistors in a bipolar region of a substrate can undesirably affect fabrication of CMOS transistors in a CMOS region of the substrate. As a result, manufacturing yield can undesirably decrease, which causes a corresponding increase in manufacturing cost. Thus, semiconductor manufacturers are challenged to provide a process for fabricating bipolar transistors in a bipolar region of a substrate that does not undesirably affect CMOS devices in a CMOS region of the substrate.
In one known technique utilizing a “polysilicon process flow,” an emitter window stack is formed over a SiGe base layer in bipolar and CMOS regions of a substrate. The emitter window stack includes a thin base oxide layer, an antireflective coating (“ARC”) layer, and a layer of amorphous polysilicon (“poly”), which are sequentially deposited over the SiGe base layer. After patterning and etching an emitter window in the emitter window stack in the bipolar region of the substrate, a layer of emitter poly is deposited in the emitter window opening and over the SiGe base layer. An emitter is then formed in an emitter poly etch process, which requires selective removal of the emitter poly layer, ARC layer, amorphous poly layer, and thin base oxide layer in the bipolar and CMOS regions of the substrate. The selective removal of the amorphous poly layer, in addition to removal of the other layers discussed above, undesirably increases complexity of the emitter poly etch process.
Although the “poly process flow” discussed above achieves desirable control of emitter window critical dimension, the poly process flow is a complex process that requires removal of multiple layers in bipolar and CMOS regions of the substrate. Furthermore, the poly process flow requires fabrication of an additional poly layer, i.e. an amorphous poly layer, which undesirably increases overall processing time. Additionally, the poly process flow causes defects, such as pitting and poly stringer formation, in CMOS region of the substrate, which reduce manufacturing yield and increase manufacturing cost.
Thus, there is need in the art for a method for fabricating bipolar transistors in a BiCMOS process that provides reduced process complexity and manufacturing cost.